1. Technical Field
The invention relates in general to integrated circuit technology and more particularly to a design for clock generation devices used in integrated circuit microprocessors. In particular the invention relates to clock generation devices utilized in CMOS microprocessor integrated circuits. Still more particularly, the invention relates to clock generation devices which utilize a differential SAW (Surface Acoustic Wave) oscillator or an ordinary crystal oscillator as a clock frequency source, and which provides negligible jitter, improvements in cycle time, and which is primarily digital in nature.
2. Description of the Related Art
A clock generation design that produces less jitter than is currently available in monolithic PLL (Phase-Locked Loop) designs of noisy microprocessor CMOS chips is a goal sought by integrated circuit designers. A PLL is a system that uses feedback to maintain an output signal in specific phase relationship with a reference signal. PLLs are used in many areas of electronics to control the frequency and/or phase of a signal. These applications include frequency synthesizers, analog and digital modulators and demodulators, and clock recovery circuits.
In the design of integrated microprocessor circuits utilizing dynamic circuits, it is highly desirable to employ circuits having low jitter. Jitter is any vibration or fluctuation in a given signal. In television and computer monitors, for example, jitter is often visible in horizontal lines that are the same thickness as scan lines. In integrated circuit devices, jitter is often the result of supply noise and substrate noise. In high-resolution graphic display devices utilizing PLL designs, the jitter performance of PLLs limits the system performance. Power-supply noise coupling is a major cause of PLL jitter problems, especially with low-supply voltages and with multiple clock synthesizers on the same device.
The use of PLLs for microprocessor clock generation is well known in the art of integrated circuits. For PLLs that are on the same chip as a high-performance microprocessor, the power supply switching noise of the digital circuits (i.e. 10% of the supply voltage) is the major noise source for output jitter. To reduce jitter, the power supply noise rejection of analog circuits inside the PLL must be maximized. For low-power PLLs, a second jitter source is the intrinsic noise of MOS devices in the VCO (Voltage Controlled Oscillator). A VCO is a circuit that produces an AC output signal whose frequency is proportional to the input control voltage. This noise can be reduced by increasing the power consumption.
To obtain low-voltage analog circuits, the saturation voltage of MOS devices needs to be reduced by using wider devices. This results in a larger parasitic capacitance between the supply voltage and the analog nodes, decreasing the power supply noise rejection for the same current consumption. The challenge in using PLLs for microprocessor clock generation is to design a PLL which combines limited jitter, low-supply voltage and low-power consumption. Despite improvements in reducing jitter in PLL based systems, current state of the art PLL based systems only manage jitter and skew sums in the range of 200-300 ps (picoseconds). An alternative to strictly PLL based systems is the addition of a SAW (Surface Acoustic Wave) oscillator to such PLL based systems.
A SAW, also called a Rayleigh wave, is composed of a coupled compressional and shear wave in which the SAW energy is confined near the surface. There is also an associated electrostatic wave for a SAW on a piezoelectric substrate which allows electroacoustic coupling via a transducer. Two key advantages of SAW technology are its ability to electroacoustically access and tap the wave at the crystal surface and a wave velocity approximately 10,000 times slower than an electromagnetic wave. There are a large number of materials which are currently being used for SAW devices. The most popular materials are quartz, lithium niobate, and lithium tantalate.
Crystal oscillators are today at the heart of every clock that does not derive its reference frequency from an AC power line. They are also used in color television sets and personal computers. In these applications at least one (or more) "quartz crystal" controls frequency or time, which explains the label "quartz" which appears on many clocks and watches.
Current SAW oscillators have jitter values of 10-20 ps (picoseconds) with 200 mv of power supply noise. Jitter reduction results in two major benefits at the system level. A jitter reduction of 10X results in increased system performance over current best of breed PLLs. Second, long term accumulation of cycle to cycle jitter as a function of power supply or substrate fluctuations, which results in the accumulation of errors, is reduced allowing for faster chip to chip I/O transfers where long term jitter is an increased factor. These benefits are particularly enhanced in multiphase clock systems.
A typical SAW oscillator utilized in the electronics industry today is the SC0017A 400 MHz Differential-Sinewave Clock manufactured by RF Monolithics, Inc. (RFM.RTM.). This device is a quartz based oscillator which provides SAW frequency stability. A fundamental fixed frequency and very low jitter and power consumption are hallmarks of the device. The digital clock is designed for use with high speed CPUs and digitizers. Fundamental oscillation is made possible by utilizing SAW technology. Current SAW oscillators are fabricated in the 100 to 800 MHz range for minimal cost. This is the range of current microprocessor clock frequencies.
The difficulty in utilizing SAW oscillators with clock generation devices is that such SAW based devices must replace conventional PLL systems. Conventional PLL systems operate with internal oscillation devices. A SAW based device, in order to provide varying frequencies, would be external to the system. In essence, a PLL clock generation circuit must be designed with the SAW oscillator in mind.
PLL systems are typically synchronized in CMOS microprocessors to a master reference clock, allowing for the addition of multiple processors and maintaining a common synchronization boundary. PLL systems designed today are also typically analog based. However, such analog devices provide a great deal of jitter, whether positive or negative. A digital PLL clock generation system which is primarily digital in nature will allow for reduced or negligible jitter. Such digital systems are uncommon and difficult to implement. Designing a PLL based clock generation circuit having minimal or negligible jitter which utilizes an external SAW oscillator is a desirable design goal, one sought by designers in the integrated electronics industry today.